Programmable memory decode circuits with transistors with vertical gates

ABSTRACT

Structures and methods for programmable memory decode circuits are provided with logic cells, or floating gate transistors, which can operate with lower applied control gate voltages than conventional memory decode circuits. The programmable logic arrays of the present invention do not increase the costs or complexity of the fabrication process. According to the teachings of the present invention, the floating gate capacitance in the logic cells is much smaller than the control gate capacitance such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide. The memory decode circuits include a number of address lines and a number of output lines such that the address lines, and the output lines form an array. A number logic cells are disposed at the intersections of output lines and address lines. A number of non volatile memory cells are disposed at the intersections of the address lines and at least one redundant output line. The number of non volatile memory cells include a source region, a drain region, and channel region separating the source and the drain regions in a horizontal substrate. A first vertical gate is located above a portion of the channel region and separated from the channel region by a first thickness insulator material. A second vertical gate is located above another portion of the channel region and separated therefrom by a second thickness insulator material.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending, commonlyassigned U.S. patent applications: “Horizontal Memory Devices withVertical Gates,” Ser. No. 09/584,566, and “Programmable Logic Arrayswith Transistors with Vertical Gates,” Ser. No. 09/583,584, which arefiled on even date herewith and each of which disclosure is hereinincorporated by reference.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuits and inparticular to programmable memory address and decode circuits withtransistors having vertical gates.

BACKGROUND OF THE INVENTION

One difficulty with memory address and decode circuit transistors is theone time programmability of the metal oxide semiconductor field effecttransistors (MOSFETs) used in such a conventional array. Anotherdifficulty is that when floating gate transistors are used to afford inthe field, or in service programmability to the array such floating gatetransistors generally require high operating and high programmingvoltages which are not well suited to low power applications. Thesefloating gate transistors can be EEPROM, EAPROM, and flash memory celltypes. One reason for the high operating and high programming voltagerequirements in these floating gate transistors is the adversecapacitance ratio between the control gate and the floating gate. Inother words, the capacitance between the control gate to floating gate(CCG) is about the same as the floating gate to substrate capacitance(CFG). FIG. 1A is an illustration of a horizontal EEPROM, EAPROM, orflash memory device formed according to the teachings of the prior art.As shown in FIG. 1A, conventional horizontal floating gate transistorstructures include a source region 110 and a drain region 112 separatedby a channel region 106 in a horizontal substrate 100. A floating gate104 is separated by a thin tunnel gate oxide 105 shown with a thickness(t1). A control gate 102 is separated from the floating gate 104 by anintergate dielectric 103 shown with a thickness (t2). Such conventionaldevices must by necessity have a control gate 102 and a floating gate104 which are about the same size in width.

FIG. 1B is an illustration of a vertical EEPROM, EAPROM, or flash memorydevice formed according to the disclosure in a co-pending, commonlyassigned application by W. Noble and L. Forbes, entitled “Fieldprogrammable logic array with vertical transistors,” Ser. No.09/032,617, filed Feb. 27, 1998. FIG. 1B illustrates that verticalfloating gate transistor structures have a stacked source region 110 anddrain region 112 separated by a vertical channel region 106. Thevertical floating gate transistor shown in FIG. 1B further includes avertical floating gate 104 separated by a thin tunnel gate oxide 105from the channel region 106. A vertical control gate 102 is separatedfrom the floating gate 104 by an intergate dielectric 103. As shown inFIG. 1B, the vertical control gate 102 and the vertical floating gate104 are likewise about the same size in width relative to the channelregion 106.

Conventionally, the insulator, or intergate dielectric, 103 between thecontrol gate 102 and the floating gate 104 is thicker (t2) than the gateoxide 105 (t1) to avoid tunnel current between the gates. The insulator,or intergate dielectric, 103 is also generally made of a higherdielectric constant insulator 103, such as silicon nitride or siliconoxynitride. This greater insulator thickness (t2) tends to reducecapacitance. The higher dielectric constant insulator 103, on the otherhand, increases capacitance. As shown in FIG. 1C, the net result is thatthe capacitance between the control gate and the floating gate (CCG) isabout the same as the gate capacitance of the thinner gate tunnelingoxide 105 between the floating gate and the substrate (CFG). Thisundesirably results in large control gate voltages being required fortunneling, since the floating gate potential will be only about one halfthat applied to the control gate.

As design rules and feature size (F) in floating gate transistorscontinue to shrink, the available chip surface space in which tofabricate the floating gate also is reduced. In order to achieve ahigher capacitance between the control gate and floating gate (CCG) somedevices have used even higher dielectric constant insulators between thecontrol gate and floating gate. Unfortunately, using such higherdielectric constant insulators involves added costs and complexity tothe fabrication process.

Therefore, there is a need in the art to provide field programmablememory address and decode circuits which can operate with lower controlgate voltages and which do not increase the costs or complexity of thefabrication process. Further such devices should desirably be able toscale with shrinking design rules and feature sizes in order to provideeven higher density integrated circuits.

SUMMARY OF THE INVENTION

The above mentioned problems with field programmable memory address anddecode circuits and other problems are addressed by the presentinvention and will be understood by reading and studying the followingspecification. Structures and methods for field programmable memoryaddress and decode circuits are provided with logic cells, or floatinggate transistors, which can operate with lower applied control gatevoltages than conventional field programmable memory address and decodecircuits. The field programmable memory address and decode circuits ofthe present invention do not increase the costs or complexity of thefabrication process. These circuits and methods are fully scalable withshrinking design rules and feature sizes in order to provide even higherdensity integrated circuits. The total capacitance of the logic cellswithin the field programmable memory address and decode circuits isabout the same as that for the prior art of comparable source and drainspacings. However, according to the teachings of the present invention,the floating gate capacitance in the logic cells is much smaller thanthe control gate capacitance such that the majority of any voltageapplied to the control gate will appear across the floating gate thintunnel oxide. Thus, the logic cells in the programmable memory addressand decode circuits of the present invention can be programmed bytunneling of electrons to and from the silicon substrate at lowercontrol gate voltages than is possible in the prior art.

In one embodiment of the present invention an address decoder for amemory device is provided. The address decoder includes a number ofaddress lines and a number of output lines. The address lines and theoutput lines form an array. A number logic cells that are disposed atthe intersections of output lines and address lines. Further, a numberof non volatile memory cells are disposed at the intersections of theaddress lines and at least one output line. In one embodiment, the atleast one output line includes a redundant output line. According to theteachings of the present invention, the number of non volatile memorycells include a source region, a drain region, and a channel regionseparating the source and the drain regions in a horizontal substrate. Afirst vertical gate is located above a portion of the channel region andseparated from the channel region by a first thickness insulatormaterial. A second vertical gate is located above another portion of thechannel region and separated therefrom by a second thickness insulatormaterial. The second vertical gate opposes the first vertical gate, andis separated from the first vertical gate by an intergate dielectric.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is an illustration of a horizontal EEPROM, EAPROM, or flashmemory device formed according to the teachings of the prior art.

FIG. 1B is an illustration of a vertical EEPROM, EAPROM, or flash memorydevice formed according to the teachings of the existing art.

FIG. 1C is a schematic diagram illustrating the generally equivalentcapacitances of the control gate (CCG) and the floating gate (CFG)according to the existing art.

FIG. 2A is a block diagram of an embodiment for a novel memory cell,transistor, or floating gate transistor formed according to theteachings of the present invention.

FIG. 2B is a schematic diagram illustrating the respective capacitancesbetween the between respective components of the novel memory cell shownin FIG. 2A.

FIG. 2C is a simplified schematic diagram representing the samecapacitance relationship shown in FIG. 2B.

FIG. 3A is a block diagram of another, asymmetrical embodiment for anovel memory cell, transistor, or floating gate transistor formedaccording to the teachings of the present invention.

FIG. 3B is a schematic diagram illustrating the respective capacitancesbetween the between respective components of the novel memory cell shownin FIG. 3A.

FIG. 3C is a simplified schematic diagram representing the samecapacitance relationship shown in FIG. 3B.

FIGS. 4A-4I illustrate embodiments of the methods for forming the novelmemory cell, transistor or floating gate transistor according to theteachings of the present invention.

FIGS. 5A-5E are block diagrams illustrating embodiments of the methodsfor operating the novel memory cells of the present invention.

FIG. 6 shows a conventional NOR decode array for memory circuitsaccording to the teachings of the prior art.

FIG. 7 is a schematic diagram illustrating an embodiment of a decodecircuit, or memory address decoder, according to the teachings of thepresent invention.

FIG. 8 is a simplified block diagram of a high-level organization of anelectronic system according to the teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include any structure havingan exposed surface with which to form the integrated circuit (IC)structure of the invention. The term substrate is understood to includesemiconductor wafers. The term substrate is also used to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art. The termconductor is understood to include semiconductors, and the terminsulator is defined to include any material that is less electricallyconductive than the materials referred to as conductors. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims, along with the full scope of equivalents to which such claimsare entitled.

FIG. 2A is a block diagram of an embodiment for a novel memory cell,transistor, or floating gate transistor 201 formed according to theteachings of the present invention. As shown in FIG. 2A, the memory cell201 includes a source region 210 and a drain region 212 separated by achannel region 206 in a horizontal substrate 200. According to theteachings of the embodiment shown in FIG. 2A, the memory cell 201includes a first vertical gate 202 located above a first portion, orfirst region, 207-1, of the channel region 206. In one embodiment, thefirst vertical gate 202 includes or serves as a floating gate 202 forthe memory cell 201. In an alternative embodiment, the first verticalgate 202 includes or serves as a control gate 202 for memory cell 201.The first vertical gate is separated from the channel region 206 by afirst thickness insulator material, or first oxide thickness (t1). Asecond vertical gate 204A is located above a second portion, or secondregion, 207-2 of the channel region 206. The second vertical gate 204Ais separated from the channel region 206 by a second thickness insulatormaterial, or second oxide thickness (t2). The memory cell 201 embodimentshown in FIG. 2A further includes a third vertical gate 204C locatedabove a third portion, or third region, 207-3 of the channel region 206.The third vertical gate is separated from the channel region 206 by thesecond thickness insulator material, or second oxide thickness (t2). Inone embodiment of the present invention, the first oxide thickness (t1)is approximately 60 Angstroms (Å) and the second oxide thickness (t2) isapproximately 100 Angstroms (Å). According to the teachings of thepresent invention, the first thickness insulator material (t1) and thesecond thickness insulator material (t2) are formed of silicon dioxide(SiO₂).

As shown in the embodiment of FIG. 2A, the second and the third verticalgates, 204A and 204C respectively, are parallel to and on opposing sidesof the first vertical gate 202 forming a symmetrical structure. Thememory cell 201 embodiment of FIG. 2A further includes a horizontal gatemember 204B which couples the second 204A and the third 204C verticalgates. The horizontal gate member 204B is located above the firstvertical gate 202 and separated therefrom by an intergate dielectric203. In the embodiment shown in FIG. 2A, the second and the thirdportion, 207-2 and 207-3 respectively, of the channel region 206 areadjacent to the source region 210 and the drain region 212 respectively.

According to one embodiment of the present invention, the first verticalgate 202, the second vertical gate 204A, the horizontal gate member204B, and the third vertical gate 204C include polysilicon gates whichare separated from one another by the intergate dielectric 203.According to the teachings of the present invention, the intergatedielectric includes an intergate dielectric formed from silicon dioxide(SiO₂). In one embodiment, the intergate dielectric 203 between thefirst vertical gate 202, the second vertical gate 204A, the horizontalgate member 204B, and the third vertical gate 204C has a thicknessapproximately equal to the first oxide thickness (t1), or firstthickness insulator material. In one embodiment of the presentinvention, the first vertical gate 202, the second vertical gate 204A,and the third vertical gate 204C each have a horizontal width ofapproximately 100 nanometers (nm).

As described above, in one embodiment, the first vertical gate 202 inmemory cell 201 serves as a floating gate 202. In this embodiment, thesecond vertical gate 204A, the horizontal gate member 204B, and thethird vertical gate 204C serve as control gates. In an alternativeembodiment, the first vertical gate 202 in memory cell 201 serves as acontrol gate for the memory cell 201. In this embodiment, the secondvertical gate 204A, the horizontal gate member 204B, and the thirdvertical gate 204C serve as floating gates. In one embodiment, the firstvertical gate 202, the second vertical gate 204A, and the third verticalgate 204C have a vertical height, respectively, of approximately 500nanometers (nm).

FIG. 2B is a schematic diagram illustrating the respective capacitancesbetween the between the first vertical gate 202, the second verticalgate 204A, the horizontal gate member 204B, and the third vertical gate204C, e.g. the control gate capacitance (CCG), as well as between thesevertical gates and the channel region 206, e.g. the floating gatecapacitance (CFG). FIG. 2C is a simplified schematic diagramrepresenting the same capacitance relationship. Thus, according to theteachings of the present invention, a greater percentage of a voltageapplied to the control gate appears between the floating gate and thechannel than between the control gate and the floating gate. This istrue, since as shown in FIGS. 2B and 2C, the floating gate capacitance(CFG) of the present invention is much smaller than the control gatecapacitance (CCG).

According to the teachings of the present invention, the totalcapacitance of these memory devices is about the same as that for theprior art of comparable source and drain spacings. However, according tothe teachings of the present invention, the floating gate capacitance ismuch smaller than the control gate capacitance such that the majority ofany voltage applied to the control gate will appear across the floatinggate thin tunnel oxide. Thus, the devices of the present invention canbe programmed by tunneling of electrons to and from the siliconsubstrate at lower control gate voltages than is possible in the priorart.

FIG. 3A is a block diagram of another, asymmetrical embodiment for anovel memory cell, transistor, or floating gate transistor 301 formedaccording to the teachings of the present invention. As shown in FIG.3A, the memory cell 301 includes a source region 310 and a drain region312 separated by a channel region 306 in a horizontal substrate 300.According to the teachings of the embodiment shown in FIG. 3A, thememory cell 301 includes a first vertical gate 302 located above a firstportion, or first region, 307-1, of the channel region 306. In oneembodiment, the first vertical gate 302 includes or serves as a verticalfloating gate 302 for the memory cell 301. In an alternative embodiment,the first vertical gate 302 includes or serves as a vertical controlgate 302 for memory cell 301. The first vertical gate is separated fromthe channel region 306 by a first thickness insulator material, or firstoxide thickness (t1). A second vertical gate 304A is located above asecond portion, or second region, 307-2 of the channel region 306. Thesecond vertical gate 304A is parallel to and opposes the first verticalgate 302 and is separated therefrom by an intergate dielectric 303. Thesecond vertical gate 304A is separated from the channel region 306 by asecond thickness insulator material, or second oxide thickness (t2).According to the teachings of the present invention, the first thicknessinsulator material (t1) and the second thickness insulator material (t2)are formed of silicon dioxide (SiO₂). In one embodiment, the firstthickness insulator material (t1) is approximately 60 Angstroms (Å), andwherein the second thickness insulator material (t2) is approximately100 Angstroms (Å).

According to one embodiment of the present invention, the secondvertical gate 304A includes a horizontal gate member 304B which couplesto the second vertical gate 304A and is separated from the firstvertical gate by the intergate dielectric 303. As shown in FIG. 3A, thehorizontal member 304B is located above a portion of the first verticalgate 302. According to the teachings of the present invention, theintergate dielectric includes an intergate dielectric formed fromsilicon dioxide (SiO₂). In one embodiment, the intergate dielectric 303between the first vertical gate 302, the second vertical gate 304A, andthe horizontal gate member 304B has a thickness approximately equal tothe first oxide thickness (t1), or first thickness insulator material.In one embodiment of the present invention, the first vertical gate 302and the second vertical gate 304A each have a horizontal width ofapproximately 100 nanometers (nm). In one embodiment, the first verticalgate 302 and the second vertical gate 304A respectively each have avertical height of approximately 500 nanometers (nm).

As shown in FIG. 3A, the first vertical gate 302 which is separated froma first portion 307-1 of the channel region is separated from a firstportion 307-1 of the channel region 306 which includes a portion of thechannel region 306 adjacent to the source region 310. The secondvertical gate 304A which is separated from a second portion 307-2 of thechannel region 306 is separated from a second portion 307-2 of thechannel region which includes a portion of the channel region 306adjacent to the drain region 312. As one of ordinary skill in the artwill understand upon reading this disclosure, the relationship of thestructure shown in FIG. 3A to the source and drain regions, 310 and 312respectively, can be reversed. As shown in FIG. 3A, in one embodiment ofthe present invention, source and/or drain region extension, such assource extension 311, are included in memory cell 301. As will beunderstood by one of ordinary skill in the art upon reading thisdisclosure, the same can apply to the memory cell structure shown inFIG. 2A.

FIG. 3B is a schematic diagram illustrating the respective capacitancesbetween the between the first vertical gate 302, the second verticalgate 304A, and the horizontal gate member 304B, e.g. the control gatecapacitance (CCG), as well as between these vertical gates and thechannel region 306, e.g. the floating gate capacitance (CFG). FIG. 3C isa simplified schematic diagram representing the same capacitancerelationship. Thus, according to the teachings of the present invention,a greater percentage of a voltage applied to the control gate appearsbetween the floating gate and the channel than between the control gateand the floating gate. This is true, since as shown in FIGS. 3B and 3C,the floating gate capacitance (CFG) of the present invention is muchsmaller than the control gate capacitance (CCG). In other words, acapacitance between the vertical control gate 304A and the floating gate302 (CCG) is greater than a capacitance between the floating gate 302and the channel 306 (CFG).

Hence again, according to the teachings of the present invention, thetotal capacitance of these memory devices is about the same as that forthe prior art of comparable source and drain spacings. However,according to the teachings of the present invention, the floating gatecapacitance is much smaller than the control gate capacitance such thatthe majority of any voltage applied to the control gate will appearacross the floating gate thin tunnel oxide. Thus, the devices of thepresent invention can be programmed by tunneling of electrons to andfrom the silicon substrate at lower control gate voltages than ispossible in the prior art.

FIGS. 4A-4I are useful in illustrating the methods of forming a novelmemory cell, transistor or floating gate transistor according to theteachings of the present invention. According to the teachings of thepresent invention an edge-defined poly-silicon vertical gate is definedover the thin gate oxide in the active device area. This vertical gateis re-oxidized and another poly-silicon layer is deposited over thestructure, and anisotropically or directionally etched to define anotherpolysilicon vertical gate. These can be either symmetrical gatestructures as shown and described in connection with FIG. 2A orasymmetrical gate structures as shown and described in connection withFIG. 3A. The methods of the present invention result in a novel memorycell which has a larger capacitance between the control gate and thefloating gate, and only a smaller capacitance between the floating gateand the substrate. Thus, according to the teachings of the presentinvention, smaller control gate voltages than are required byconventional memory devices will result in large potential differencesbetween the floating gate and substrate. This is due to the fact thatthe capacitance ratio as illustrated in FIGS. 2B, 2C, 3B, and 3C is moreadvantageous in the novel memory cell embodiments of the presentinvention.

FIG. 4A illustrates the structure after the first sequence of processingsteps. In FIG. 4A, a thin gate oxide 401 is formed over an active devicearea 404, between a pair of field isolation oxides (FOXs) 420, in ahorizontal surface of a substrate 400. The thin gate oxide 401 is formedto a first oxide thickness (t1). In one embodiment, the thin gate oxide401 is formed to a thickness (t1) of approximately 60 Angstroms (Å). Oneof ordinary skill in the art will understand upon reading thisdisclosure the various suitable manners in which a thin gate oxide 401can be formed over the active device area 403. For example, in oneembodiment, the thin gate oxide can be formed by thermal oxidation, andthe FOXs can be formed using local oxidation of silicon (LOCOS) as thesame are known and understood by one of ordinary skill in the art. Aftergrowth of the thin gate oxide 401 by thermal oxidation, and the LOCOSisolation 420, a thick layer of sacrificial oxide 402 is deposited overthe surface of the thin gate oxide 401. In one embodiment, the thicklayer of sacrificial oxide 402 is deposited to a thickness ofapproximately 0.5 micrometers (μm) using a low-pressure chemical vapordeposition (LPCVD) technique. Using a photoresist mask, according tophotolithography techniques which are known and understood by one ofordinary skill in the art, this thick oxide 402 is etched. The desiredthin-oxide 401 can be regrown in the areas not covered by the remainingthick sacrificial oxide 402. According to one embodiment of the presentinvention, an inductively coupled plasma reactor (ICP) using CHF₃ may beemployed for this etching as the same is disclosed in an article by N.R.Rueger et al., entitled “Selective etching of SiO₂ over polycrystallinesilicon using CHF₃ in an inductively couples plasma reactor”, J. Vac.Sci. Technol., A, 17(5), p. 2492-2502, 1999. Alternatively, a magneticneutral loop discharge plasma can be used to etch the thick oxide 402 asdisclosed in an article by W. Chen et al., entitled “Very uniform andhigh aspect ratio anisotropy SiO₂ etching process in magnetic neutralloop discharge plasma”, ibid, p. 2546-2550. The latter is known toincrease the selectivity of SiO₂ to photoresist and/or silicon. Thestructure is now as appears in FIG. 4A.

FIG. 4B illustrates the structure following the next sequence offabrication steps. In FIG. 4B, a polysilicon layer 406 is deposited to athickness of approximately 200 nanometers (nm). A conventional chemicalvapor deposition (CVD) reactor may be used to deposit polycrystallinesilicon films at substrate temperature in excess of 650° Celsius (C). Inan alternative embodiment, a plasma-enhanced CVD process (PECVD) can beemployed if a lower thermal budget is desired. In another alternativeembodiment, a microwave-excited plasma enhanced CVD of poly-siliconusing SiH₄/Xe at temperature as low as 300° C. can be performed todeposit the polysilicon layer 406 as disclosed by Shindo et al., ibid.p. 3134-3138. According to this process embodiment, the resulting grainsize of the polysilicon film was measured to be approximately 25 nm.Shindo et al. claim that the low-energy (approximately 3 eV), high-flux,ion bombardment utilizing Xe ions on a growing film surface activatesthe film surface and successfully enhances the surfacereaction/migration of silicon, resulting in high quality film formationat low temperatures. In another alternative embodiment, the polysiliconlayer 406 can be formed at an even lower temperature, e.g. 150° C., withand without charged species in an electron cyclotron resonance (ECR)plasma-enhanced CVD reactor as disclosed in an article by R. Nozawa etal., entitled “Low temperature polycrystalline silicon film formationwith and without charged species in an electron cyclotron resonance SiH₄plasma-enhanced chemical vapor deposition”, ibid, p. 2542-2545. In thisarticle, R. Nozawa et al. describe that in using an atomic forcemicroscope they found that the films formed without charged species weresmoother than those films formed with charged species. According to theteachings of the present invention, it is important to keep thesmoothness of polysilicon layer 406. This will be evident from readingthe subsequently described process steps in which another polysiliconlayer will be fabricated later onto polysilicon layer 406 with a verythin insulation layer between them. The structure is now as appears inFIG. 4B.

FIG. 4C illustrates the structure following the next sequence ofprocessing steps. FIG. 4C shows a cross section of the resultingvertical gate structures, 407A and 407B, over the active device area 404after the polysilicon layer 406 has been anisotropically etched. Asshown in FIG. 4C, the polysilicon vertical gate structures, 407A and407B, remain only at the sidewalls of the thick sacrificial oxide 402.In one embodiment, the polysilicon layer 406 is anisotropically etchedsuch that the vertical gate structures, 407A and 407B remaining at thesidewalls of the thick sacrificial oxide 402 have a horizontal width(W1) of approximately 100 nanometers (nm). In one embodiment, thepolysilicon layer 406 can be anisotropically etched to form the verticalgate structures, 407A and 407B, through the use of a high-density plasmahelicon source for anisotropic etching of a dual-layer stack ofpoly-silicon on Si_(1−x)Ge_(x), as described in an article by Vallon etal., entitled “Poly-silicon-germanium gate patterning studies in a highdensity plasma helicon source”, J. Vac. Sci. technol., A, 15(4), p.1874-80, 1997. The same is incorporated herein by reference. In thisarticle, wafers were described as being etched in a low pressure, highdensity plasma helicon source using various gas mixtures of Cl₂, HBr,and O₂. Also, according to this article, process conditions wereoptimized to minimize the gate oxide 401 consumption. The structure isnow as shown in FIG. 4C.

FIG. 4D illustrates the structure after the next series of processsteps. In FIG. 4D, the thick sacrificial oxide 402 is removed. As one ofordinary skill in the art will understand upon reading this disclosurethe thick sacrificial oxide layer can be removed using any suitable,oxide selective etching technique. As shown in FIG. 4D, the remainingpolysilicon vertical gate structures, 407A and 407B, are oxidized toform insulator, intergate dielectric, oxide layer, or silicon dioxide(SiO₂) layer 409. In one embodiment, a conventional thermal oxidation ofsilicon may be utilized at a high temperature, e.g. greater than 900° C.In an alternative embodiment, for purposes of maintaining a low thermalbudget for advanced ULSI technology, a lower temperature process can beused. One such low temperature process includes the formation ofhigh-quality silicon dioxide films by electron cyclotron resonance (ECR)plasma oxidation at temperature as low as 400° C. as described in anarticle by Landheer, D. et al., entitled “Formation of high-qualitysilicon dioxide films by electron cyclotron resonance plasma oxidationand plasma-enhanced chemical vapor deposition”, Thin Solid Films, vol.293, no. 1-2, p. 52-62, 1997. The same is incorporated herein byreference. Another such low temperature process includes a lowtemperature oxidation method using a hollow cathode enhanced plasmaoxidation system as described in an article by Usami, K. et al.,entitled “Thin Si oxide films for MIS tunnel emitter by hollow cathodeenhanced plasma oxidation”, Thin Solid Films, vol. 281-282, no. 1-2, p.412-414, 1996. The same is incorporated herein by reference. Yet anotherlow temperature process includes a low temperature VUV enhanced growthof thin silicon dioxide films at low temperatures below 400° C. asdescribed in an article by Patel, P. et al., entitled “Low temperatureVUV enhanced growth of thin silicon dioxide films”, Applied SurfaceScience, vol. 46, p. 352-6, 1990. The same is incorporated herein byreference.

FIG. 4E shows the structure following the next series of steps. In FIG.4E, another, or second, polysilicon layer 411 is formed over the oxidelayer 409 to a thickness of approximately 100 nm. Forming the secondpolysilicon layer 411 over the oxide layer 409 can be performed usingany similar technique to those used in forming the first polysiliconlayer 406 as described in detail in connection with FIG. 4B. As shown inFIG. 4E, the second polysilicon layer 411 will be separated by a secondoxide thickness, or second insulator thickness (t2) from the activedevice region 404 which is slightly greater than the thin tunnel oxidethickness, e.g. first oxide thickness or first insulator thickness (t1)which separates the vertical gate structures 407A and 407B from thesubstrate 400. In one embodiment the second oxide thickness, or secondinsulator material thickness (t2) is approximately 100 Angstroms (Å)thick. The structure is now as appears in FIG. 4E.

FIG. 4F illustrates the structure after the next series of steps. InFIG. 4F, the structure is once again subjected to an anisotropic etch.The anisotropic etch includes the anisotropic etching process used foretching the first polysilicon layer 406 to form the vertical gatestructures 407A and 407B as described in more detail in connection withFIG. 4C. FIG. 4F shows one embodiment of the present invention in whichthe resulting structure is symmetrical, including two groups of threefree standing vertical polysilicon gates. The two groups of three freestanding vertical gates include the original vertical gate structures407A and 407B, and new vertical gate structures 413A and 413B parallelto and on opposing sides of each original vertical gate structures 407Aand 407B. This structure embodiment is now as appears in FIG. 4F.

In FIG. 4G, the process is continued to form horizontal polysilicon gatestructures above the original vertical gate structures 407A and 407B,and new vertical gate structures 413A and 413B on opposing sides of eachoriginal vertical gate structures 407A and 407B. In FIG. 4G, the newvertical gate structures 413A and 413B are connected by forming a thirdpolysilicon layer 415 over a top surface of the structure shown in FIG.4F. The third polysilicon layer 415 can be formed over the top surfaceof the structure shown in FIG. 4F using any similar technique to thoseused in forming the first polysilicon layer 406 as described in detailin connection with FIG. 4B. In one embodiment, according to theteachings of the present invention, the third polysilicon layer 415 isformed to a thickness of approximately 100 nm. In one embodiment,forming the third polysilicon layer 415 is followed by masking andetching techniques, as the same have been described above, in order toleave horizontal polysilicon gate structures 415 only above andconnecting the vertical gate structures 413A and 413B. The structure isnow as appears in FIG. 4G. FIG. 4G thus represent a symmetricalstructure embodiment of the present invention in which the vertical gatestructures 413A and 413B, which are parallel to and on opposing sides ofeach vertical gate structures 407A and 407B, are coupled by thehorizontal polysilicon gate structures 415 above the vertical gatestructures 407A and 407B. As shown in FIG. 4G, the vertical gatestructures 413A and 413B coupled by the horizontal polysilicon gatestructures 415 are isolated from vertical gate structures 407A and 407Bby insulator layer or oxide layer 409.

In one embodiment, illustrated by FIG. 4H, the structure of FIG. 4G canbe anisotropically etched using masking techniques known to one ofordinary skill in the art, as well as the anisotropic etching processesdescribed in connection with FIG. 4F, to produce asymmetrical verticalgate structures. These asymmetrical vertical gate structures willinclude the original vertical gate structures 407A and 407B, and oneremaining vertical gate structure, either 413A or 413B on one side or heother of each original vertical gate structures 407A and 407B as well asa horizontal gate structure 415 depending on the chosen condition of theanisotropic etch process. That is, the anisotropic etch can be performedto leave horizontal gate structure 415 coupled to and above eithervertical gate structure 413A or 413B on one side or the other of eachoriginal vertical gate structures 407A and 407B. The same is shown inFIG. 4H.

The next series of process steps can continue from either FIGS. 4G or4H. For purposes of illustration, FIG. 4I provides an illustration ofthe process steps continued from FIG. 4G. However, one of ordinary skillin the art will understand that analogous process steps may be used tocontinue the fabrication process from the structure shown in FIG. 4H. InFIG. 4I, the structure from FIG. 4G is oxidized to form an oxide layerof approximately 50 nm. The oxidation process of the structure shown inFIG. 4G can be performed using any suitable technique as the same hasbeen describe above. An ion implantation is then performed to activatesource regions shown as 410A and 410B as well as drain region 412. InFIG. 4I, the drain region 412 is illustrated as shared between verticalgate structure 407A and 407B.

One of ordinary skill in the art will understand that other source anddrain region configurations can be activated through various ionimplantation techniques. Additionally, in one embodiment, the sourceand/or drain regions can be fabricated with source and/or drainextensions, e.g. similar to source extensions shown in connection withFIG. 3A for facilitating tunneling, by using a masking step and anotherimplantation as the same is known and understood by one of ordinaryskill in the art of memory technology. Further conventional processsteps can then be used to contact the source, drain and control gateportions of the structure to complete the device of either FIG. 2A orFIG. 3A.

As described above, the structures can be completed such that verticalgates 407A and 407B serve as floating gates for the device structuresand vertical gates 413A and 413B serve as control gates. Alternatively,the structures can be completed such that vertical gates 407A and 407Bserve as a control gate for the device structures and vertical gates413A and 413B serve as floating gates.

As will be understood by reading this disclosure, the memory cells, orfloating gate transistors, of the present invention can be fabricatedsuch that the total capacitance of the device is about the same as thatof prior art horizontal or vertical floating gate transistor structures,e.g. FIGS. 1A and 1B, of comparable source/drain spacings. However, nowsince the floating gate capacitance (CFG) for the novel memory cells ofthe present invention is much smaller than the control gate capacitance(CCG) the majority of any voltage applied to the control gate willappear across the floating gate thin tunnel oxide 401. The floating gatecan then be programmed and erased by tunneling of electrons to and fromthe source of the transistor at relatively low voltages, or programmedby hot electron injection and erased by tunneling.

The operation of the novel memory cells of the present invention isillustrated in connection with FIGS. 5A-5E. As explained above, thenovel device of the present invention will function on tunneling ofelectrons to and from the source region of the device for both writingand erase operations, or operate in a tunnel-tunnel mode in conjunctionwith hot electron injection.

FIGS. 5A-5B illustrate the operation of the novel memory cell of FIG. 2Awhen the outer vertical gates serve as the control gate. In thisembodiment, the novel device 501 of the present invention will functionon tunneling of electrons to and from the channel 506 of the device 501for both writing and erase operations as the same are known andunderstood by one of ordinary skill in the art. As shown in FIG. 5A, ifno electrons are stored on the floating gate 507, then when a potentialis applied to the control gate 513, the region of the channel 511-1beneath the floating gate 507 will actually have a slightly lowerthreshold voltage (Vt) than the other regions of the channel where theslightly thicker gate oxides (t2) separate the control gate 513 from thechannel 506, and the transistor will readily turn on, at lower thanconventional control gate voltages, when a read voltage is applied tothe control gate 513. In this respect the device functions in a manneranalogous to a flash memory cell. On the other hand, as shown in FIG.5B, if electrons are stored on the floating gate 507, this region of thechannel 511-1 beneath the floating gate 507 will have a high thresholdvoltage (Vt) and will not turn on and conduct when the same low voltageis applied to the control gate 513 to read the memory cell. There aresimply no electrons in this region of the channel 511-1 beneath thefloating gate 507 to conduct.

An alternative embodiment is to interchange the functions of the gates,the inner gate 507 becoming the control gate 507 and the outer gate 513becoming the floating gate 513 as shown in FIGS. 5C-5D. In thisembodiment, as shown in FIG. 5C, again with no electrons stored on thefloating gate 513, when a potential is applied to the control gate 507,the region of the channel beneath 511-1 the control gate 507 willactually have a slightly lower threshold voltage (Vt) than the otherregions of the channel where the slightly thicker gate oxides (t2)separate the floating gate 513 from the channel 506, and the transistorwill readily turn on at lower than conventional control gate 507voltages, when a read voltage is applied to the control gate 507. On theother hand, as shown in FIG. 5D, if electrons are stored on the floatinggate 513, the other regions of the channel where the slightly thickergate oxides (t2) separate the floating gate 513 from the channel 506will have a high threshold voltage (Vt) and will not turn on and conductwhen the same low voltage is applied to the control gate 507 to read thememory cell. There are simply no electrons in these other regions of thechannel, e.g. regions 511-2 and 511-3 where the slightly thicker gateoxides (t2) separate the floating gate 513 from the channel 506, toconduct.

As shown in FIG. 5E, in this later embodiment of FIGS. 5C-5D, the eraseoperation will be performed using source side 510 tunneling. The writeoperation, however, will use hot electron injection from the channel 506at the drain region 512 to write electrons on to the floating gate 513as is commonly done in some flash memory cells. As one of ordinary skillwill understand upon reading this disclosure, similar operation modescan be employed based on the particular floating gate to control gateconfiguration selection for the structure embodiment shown in FIG. 3A.The field programmable, in service or in circuit programmable, logicdevices described here work with much lower voltages than the normaldevices used in current decode circuit technology. They can beprogrammed with Voltages of 5 to 7 Volts and the normal operatingvoltages on the control gates can be of the order 2 Volt or so. The lowprogramming voltage is a consequence of the high capacitance ratiobetween the control gate and floating gate.

FIG. 6 shows a conventional NOR decode array for memory circuits. Theaddress lines are A1 through A3 and inverse address lines, {overscore(A)}1 through {overscore (A)}3. The conventional NOR decode array isprogrammable at the gate mask level by either fabricating a thin oxidegate transistor, e.g. transistors 601-1, 601-2, . . . , 601-N, at theintersection of lines in the array or not fabricating a thin oxide gatetransistor, e.g. missing thin oxide transistors, 602-1, 602-2, . . . ,602-N, at such an intersection. As one of ordinary skill in the art willunderstand upon reading this disclosure, the same technique isconventionally used to form other types of decode arrays not shown. Asshown in FIG. 6A, a number of depletion mode NMOS transistors, 616, areused as load devices.

In this embodiment, each of the row lines 614 acts as a NOR gate for theaddress lines A1 through A3 and inverse address lines, {overscore (A)}1through {overscore (A)}3 that are connected to the row lines 614 throughthe thin oxide gate transistor, e.g. transistors 601-1, 601-2, . . . ,601-N, of the array. That is, row line R1 is maintained at a highpotential, +VDD, in the positive logic NMOS decode array shown in FIG.6A, unless one or more of the thin oxide gate transistor, e.g.transistors 601-1, 601-2, . . . , 601-N, that are coupled to row line R1are turned on by a high logic level signal, +VDD, on one of the addresslines A1 through A3 or inverse address lines, {overscore (A)}1 through{overscore (A)}3. When a transistor gate address is activated, by thehigh logic level signal, +VDD, through address lines A1 through A3 orinverse address lines, {overscore (A)}1 through {overscore (A)}3, eachthin oxide gate transistor, e.g. transistors 601-1, 601-2, . . . ,601-N, conducts, or is turned “on.” This conduction of the thin oxidegate transistor, e.g. transistors 601-1, 601-2, . . . , 601-N, performsthe NOR positive logic circuit function, an inversion of the OR circuitfunction results from inversion of data onto the row lines 614 throughthe thin oxide gate transistor, e.g. transistors 601-1, 601-2, . . . ,601-N, of the array, in order to output a low logic level signal on therow lines 614. Thus, a particular row line 614 is addressed when none ofthe thin oxide gate transistor, e.g. transistors 601-1, 601-2, . . . ,601-N, coupled to that row line 614 are turned “on.”

Again, the incoming address on each line is inverted and the combinationof the original address and inverted or complemented values used todrive the gates of transistors in the decode array 600. The transistors601-1, 601-2, . . . , 601-N in the array 600 are enhancement mode NMOSdevices and depletion mode NMOS transistors are used as load devices616. All voltages are positive in a simple NMOS circuit. This is apositive logic NOR decode array, the logic one state, “1” is the mostpositive voltage, +VDD, and the logic level zero, “0” is the leastpositive voltage or ground.

The transistors used in FIG. 6 are NMOS driver transistors with adepletion mode NMOS load technology. The load device or NMOS loadtransistor is a depletion mode or normally “on” transistor which acts asa constant current source during the pull up switching transient thusproviding high switching speed. The driver transistor is an enhancementmode NMOS transistor which is normally “off” with zero gate bias.

FIG. 7 is a schematic diagram illustrating one embodiment of a decodecircuit, or memory address decoder, 700 according to the teachings ofthe present invention. Analogous to FIG. 6, the address lines are A1through A3 and inverse address lines, {overscore (A)}1 through{overscore (A)}3. As shown in FIG. 7, the decode circuit 700 isprogrammable at the gate mask level by either fabricating a drivertransistor, or logic cell, e.g. transistors 701-1, 701-2, . . . , 701-N,at the intersection of lines in the array or not fabricating a drivertransistor, or logic cell, e.g. missing floating gate river transistors702-1, 702-2, . . . , 702-N, at such an intersection. In one embodimentaccording to the teachings of the present invention, fabricating adriver transistor, e.g. transistors 701-1, 701-2, . . . , 701-N, at theintersection of lines in the array includes fabricating the floatinggate driver transistor according to the embodiments discussed anddescribed in detail in connection with FIGS. 2A-5E. In one embodiment ofthe present invention, as shown in FIG. 7, a number of p-channel metaloxide semiconductor (PMOS) load transistors, 716, are used as loaddevices and are coupled to the output lines, or row lines, 714, of thedecode circuit 700.

The incoming address on each address line A1 through A3 is inverted andthe combination of the original address on each address line A1 throughA3 and inverted or complemented values on inverse address lines,{overscore (A)}1 through {overscore (A)}3, used to drive the gates oftransistors 701-1, 701-2, . . . , 701-N in the decode array 700. Thefloating gate driver transistors, or logic cells, e.g. transistors701-1, 701-2, . . . , 701N in the array 700 are n-channel floating gatedriver transistors.

In FIG. 7, each of the row lines 714 acts as a NOR gate for the addresslines A1 through A3 and inverse address lines, {overscore (A)}1 through{overscore (A)}3 that are connected to the row lines 714 through thefloating gate driver transistors, or logic cells, e.g. transistors701-1, 701-2, . . . , 701-N, of the array 700. That is, row line R1 ismaintained at a high potential VDD, or logic “1” unless one or more ofthe floating gate driver transistors, or logic cells, e.g. transistors701-1, 701-2, . . . , 701-N, that are coupled to row line R1 are turnedon by a high logic level signal, VDD, on one of the address lines A1through A3 or inverse address lines, {overscore (A)}1 through {overscore(A)}3. In the decode circuit 700 configuration shown in FIG. 7, a logic“1”, or VDD, on one of the address lines A1 through A3 or inverseaddress lines, {overscore (A)}1 through {overscore (A)}3, is required inorder to turn on one of the n-channel floating gate driver transistors,or logic cells, e.g. transistors 701-1, 701-2, . . . , 701-N, coupled torow line R1.

For the decode circuit 700 of the present invention, shown in FIG. 7,the driver transistors, e.g. transistors 701-1, 701-2, . . . , 701-N inthe array are floating gate transistor devices. In one embodiment, thefloating gate driver transistors 701-1, 701-2, . . . , 701 -N are formedaccording to the embodiments of the present invention as disclosed anddescribed in detail in connection with FIGS. 2A-5E. In this manner, thefloating gate driver transistors, 701-1, 701-2, . . . , 701-N, can beprogrammed initially in fabrication and can be reprogrammed as necessaryonce the decode array is in service, e.g. field programmable, toimplement a specific decode function. The load devices 716, shown in theaddress decoder 700 of FIG. 7, are p-channel metal oxide semiconductor(PMOS) transistors and not depletion mode n-channel transistors as ismore usual. In this manner, the decode circuit 700 embodiment of thepresent invention shown in FIG. 7 is formed according to a CMOS processand can be referred to as a CMOS decode array 700.

As shown in FIG. 7, the decode circuit 700 of the present inventionincludes at least one redundant row line, RD. As shown in FIG. 7, anumber of additional driver transistors, e.g. transistors T1-T6, areprovided in the array coupled to address lines A1 through A3 or inverseaddress lines, {overscore (A)}1 through {overscore (A)}3 and theredundant row line, RD. According to the teachings of the presentinvention, these additional driver transistors, e.g. transistors T1-T6,are formed according to the embodiments described and discussed indetail above in connection with FIGS. 2A-5E and as disclosed inco-filed, co-pending, commonly assigned U.S. patent application:entitled “Horizontal Memory Devices with Vertical Gates,” Ser. No.09/584,566, which disclosure is herein incorporated by reference.According to the teachings of the present invention, the additionaldriver transistors, T1-T6, will have a vertical control gate, locatedabove a horizontal channel region, coupled to address lines A1 throughA3 or inverse address lines, {overscore (A)}1 through {overscore (A)}3.The additional driver transistors, T1-T6, will further have a drainregion coupled to the at least one redundant row line, or wordline, RD.A p-channel metal oxide semiconductor (PMOS) load transistor T7, similarto p-chanel metal oxide semiconductor (PMOS) load transistors 716 iscoupled to the at least one redundant row line, RD as well to completethe CMOS inverter configuration.

As has been shown and described above, these non volatile, floating gatedriver transistors, e.g. transistors T1-T6, can be programmed to havetwo different conductivity states depending upon whether electrons arestored on the vertical floating gate. When a charge is stored on thevertical floating gate for any one of these floating gate drivertransistors, e.g. transistors T1-T6, the floating gate transistor iseffectively removed from the progranmmable memory address and decodecircuits 700 of the present invention. The implementation of thesefloating gate driver transistors, e.g. transistors T1-T6, in the decodecircuit 700 of the present invention, enables error correction forreplacing a row, or column in the array as will be explained in moredetail below.

According to the teachings of the present invention, it is desirable tohave redundant row lines, e.g. redundant row line RD, available toreplace or error correct for row lines 714, which are determineddefective or which have failed in the field. The present invention isusable to provide such error correction by replacing a row, or column,in a memory array.

One of ordinary skill in the art will understand upon reading thisdisclosure that there can be more than one redundant row line, e.g. aRD2, RD3, etc. (not shown), and similarly more additional floating gatedriver transistors, like transistors T1-T6, coupled thereto in order toenable multiple row error correction. One of ordinary skill in the artwill further understand, upon reading this disclosure, the manner inwhich the additional floating gate driver transistors, T1-T6, formedaccording to the teachings of the present invention, can be selectivelyprogrammed in order to access, or select, redundant rows RD inreplacement for any one of the output lines 714 in the decode array 700.

In summary, If electrons are stored on a vertical floating gate for oneof the additional floating gate driver transistors, T1-T6, then when ahigh input signal is received on address lines A1 through A3 or inverseaddress lines, {overscore (A)}1 through {overscore (A)}3, the“programmed floating gate driver transistor, T1-T6, will remain “off.”On the other hand, if there is no stored charge on the vertical floatinggate for that particular floating gate driver transistors, T1-T6, thenthe floating gate driver transistors, T1-T6, will conduct when a highinput signal is received on address lines A1 through A3 or inverseaddress lines, {overscore (A)}1 through {overscore (A)}3. If thefloating gate driver transistors, T1-T6, have no charge stored on thevertical floating gate they will function as normal inverters for thedecode circuit 700. Conversely, if there is a charge stored charge onthe vertical floating gate, the conductivity of the floating gate drivertransistors, T1-T6, will not become high enough and will not function asa driver transistor. In this latter case, the output for the redundantrow line RD in the decode circuit 700 of the present invention will notchange charge states. Hence, if there is a charge stored on the verticalfloating gate of the floating gate driver transistors, T1-T6, thedrivers are effectively removed from the decode circuits 700.

As one of ordinary skill in the art will further understand upon readingthis disclosure, additional inverters can be used as necessary to affectthe transition from one logic system, e.g. positive logic system, to anegative logic system while still capitalizing on the utility of thenovel floating gate driver transistors T1-T6 in decode circuit 700. Ifthe floating gate in a floating gate driver transistor is programmedwith a negative charge on the floating gate it will not be active in thearray and it is effectively removed from the array. In this manner thearray logic functions can be programmed even when the circuit is in thefinal circuit or in the field and being used in a system. The fieldprogrammable, in service or in circuit programmable, logic devicesdescribed here work with much lower voltages than the normal devicesused in current in field, or in service, programmable decode circuittechnology. They can be programmed with Voltages of 5 to 7 Volts and thenormal operating voltages on the vertical control gates can be of theorder 2 Volt or so. The low programming voltage is a consequence of thehigh capacitance ratio between the control gate and floating gate.

FIG. 8 is a simplified block diagram of a high-level organization of anelectronic system 801 according to the teachings of the presentinvention. As shown in FIG. 8, the electronic system 801 is a systemwhose functional elements consist of an arithmetic/logic unit (ALU) 820,a control unit 830, a memory unit 840 and an input/output (I/O) device850. Generally such an electronic system 801 will have a native set ofinstructions that specify operations to be performed on data by the ALU820 and other interactions between the ALU 820, the memory unit 840 andthe I/O devices 850. The memory units 840 contain the data plus a storedlist of instructions.

The control unit 830 coordinates all operations of the ALU 820, thememory unit 840 and the I/O devices 850 by continuously cycling througha set of operations that cause instructions to be fetched from thememory unit 840 and executed. Memory unit 840 can be implemented with afield programmable low voltage decode circuit, according to theteachings of the present invention, to enable error correction byreplacing a row, or column, in a memory array.

The Figures presented and described in detail above are similarly usefulin describing method of operation embodiments of the present invention.That is one method embodiment of the present invention includes a novelmethod enabling error correction in a decode circuit which has a numberof non volatile vertical floating gate transistors, or memory cells,coupled to a redundant row line. The method includes selectivelyapplying a first potential across a first thickness oxide between avertical floating gate and a first portion of a horizontal substrate inorder to add or remove a charge from the vertical floating gate. Thehorizontal substrate includes a source region and a drain regionseparated by a horizontal channel region. The method further includesenabling the redundant row line by applying a second potential to avertical control gate located above a second portion of the horizontalsubstrate. According to the teachings of the present invention, thevertical control gate is parallel to and opposing the vertical floatinggate. Selectively applying a first potential across a first thicknessoxide includes selectively applying a first potential of less than 5Volts. Selectively applying a first potential across a first thicknessoxide between a vertical floating gate and a first portion of ahorizontal substrate in order to add or remove a charge from thevertical floating gate includes controlling conduction in the horizontalchannel. Enabling the redundant row line by applying a second potentialincludes applying a second potential of approximately 2 Volts. Accordingto the teachings of the present invention, enabling the redundant rowline by applying a second potential to the vertical control gateincludes enabling the redundant row when a minimal or no charge ispresent on the vertical floating gate of the non volatile memory cellcoupled to that redundant row line.

Another method embodiment according to the teachings of the presentinvention includes a method for enabling error correction in a decodecircuit which has a number of non volatile vertical floating gatetransistors coupled to a redundant row line. This method embodimentincludes selectively storing a limited charge on a vertical floatinggate above a horizontal channel region in the number of non volatilefloating gate transistors. Selectively storing the limited charge on thevertical floating gate controls addressing the redundant row line. Themethod further includes applying a potential to a vertical control gateopposing the vertical floating gate and above the horizontal channelusing a number of address lines. Applying a potential to a verticalcontrol opposing the vertical floating gate includes applying apotential of approximately 2 Volts. Selectively storing a limited chargeon a vertical floating gate above a horizontal channel region in thenumber of non volatile floating gate transistors further includesprogramming the vertical floating gate by applying a potential of lessthan 5 Volts to the vertical control gate. Applying a potential of lessthan 5 Volts to the vertical control is such that a greater percentageof the applied potential appears between the vertical floating gate andthe horizontal channel than between the vertical floating gate and thevertical control gate. Selectively storing a limited charge on avertical floating gate above a horizontal channel region includesselectively storing a limited charge on a vertical floating gateseparated by a first oxide thickness from the horizontal channel.Applying a potential to a vertical control gate opposing the verticalfloating gate and above the horizontal channel includes applying thepotential to a vertical control gate separated by a second oxidethickness from the horizontal channel. In one embodiment, applying thepotential to the vertical control gate separated by the second oxidethickness includes applying the potential to the vertical control gateseparated by a second oxide thickness which is greater than the firstoxide thickness.

Also, according to the teachings of the present invention, the methodfurther includes selectively removing a charge from a vertical floatinggate above a horizontal channel region in the number of non volatilefloating gate transistors. As has been described, selectively storing acharge on a vertical floating gate above a horizontal channel region inthe number of non volatile floating gate transistors includes disablingthe non volatile floating gate transistor in the decode circuit.

CONCLUSION

Thus, structures and methods for field programmable memory address anddecode circuits are provided with logic cells, or floating gatetransistors, which can operate with lower applied control gate voltagesthan conventional field programmable memory address and decode circuits.The field programmable memory address and decode circuits of the presentinvention do not increase the costs or complexity of the fabricationprocess. These circuits and methods are fully scalable with shrinkingdesign rules and feature sizes in order to provide even higher densityintegrated circuits. The total capacitance of the logic cells within thefield programmable memory address and decode circuits is about the sameas that for the prior art of comparable source and drain spacings.However, according to the teachings of the present invention, thefloating gate capacitance in the logic cells is much smaller than thecontrol gate capacitance such that the majority of any voltage appliedto the control gate will appear across the floating gate thin tunneloxide. The logic cells in the programmable memory address and decodecircuits of the present invention can be programmed by tunneling ofelectrons to and from the silicon substrate at lower control gatevoltages than is possible in the prior art.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

What is claimed is:
 1. An address decoder for a memory device,comprising: a number of address lines; a number of output lines; whereinthe address lines, and the output lines form an array; a number logiccells that are disposed at the intersections of output lines and addresslines; and a number of non volatile memory cells are disposed at theintersections of the address lines and at least one output line, thenumber of non volatile memory cells including: a source region in ahorizontal substrate; a drain region in the horizontal substrate; achannel region separating the source and the drain regions; a firstvertical gate located above a portion of the channel region andseparated from the channel region by a first thickness insulatormaterial; and a second vertical gate located above another portion ofthe channel region and separated therefrom by a second thicknessinsulator material, wherein the second vertical gate opposes the firstvertical gate, and wherein the second vertical gate is separated fromthe first vertical gate by an intergate dielectric.
 2. The addressdecoder of claim 1, wherein the second vertical gate has a horizontalwidth of approximately 100 nanometers (nm).
 3. The address decoder ofclaim 1, wherein the first thickness insulator material is approximately60 Angstroms (Å), and wherein the second thickness insulator material isapproximately 100 Angstroms (Å).
 4. The address decoder of claim 1,wherein the first thickness insulator material, the second thicknessinsulator material, and the intergate dielectric include silicon dioxide(SiO₂).
 5. The address decoder of claim 1, wherein the first verticalgate has a vertical height of approximately 500 nanometers (nm) and ahorizontal width of approximately 100 Angstroms (Å).
 6. The addressdecoder of claim 1, wherein the number of non volatile memory cells thatare disposed at the intersections of the address lines and at least oneoutput line includes an output line which is a redundant row or wordline.
 7. An address decoder for a memory device, comprising: a number ofaddress lines; a number of output lines; wherein the address lines, andthe output lines form an array; a number logic cells that are disposedat the intersections of output lines and address lines; and a number ofnon volatile memory cells are disposed at the intersections of theaddress lines and at least one output line, the number of non volatilememory cells including: a source region in a horizontal substrate; adrain region in the horizontal substrate; a channel region separatingthe source and the drain regions; a first vertical gate located above aportion of the channel region and separated from the channel region by afirst thickness insulator material; and a second vertical gate locatedabove another portion of the channel region and separated therefrom by asecond thickness insulator material, wherein the second vertical gate isparallel to and opposes the first vertical gate, and wherein the secondvertical gate is separated from the first vertical gate by an intergatedielectric.
 8. The address decoder of claim 7, wherein the intergatedielectric has a thickness approximately equal to the first thicknessinsulator material.
 9. The address decoder of claim 7, wherein eachvertical gate has a vertical height of approximately 500 nanometers (nm)and a horizontal width of approximately 100 nanometers (nm).
 10. Theaddress decoder of claim 7, wherein the first thickness insulatormaterial is approximately 60 Angstroms (Å), and wherein the secondthickness insulator material is approximately 100 Angstroms (Å).
 11. Theaddress decoder of claim 7, wherein the number of non volatile memorycells that are disposed at the intersections of the address lines and atleast one output line includes programmable floating gate drivertransistors.
 12. The address decoder of claim 7, wherein the number oflogic cells that are disposed at the intersections of output lines andaddress lines includes programmable floating gate driver transistors.13. A decode circuit for a semiconductor memory, comprising: a number offloating gate transistors having a source region, a drain region, and achannel therebetween; a number of programmable logic cells, theprogrammable logic cells, comprising: a horizontal substrate, whereinthe substrate includes a source region, a drain region, and a channelregion separating the source and the drain region; a vertical floatinggate separated from a first portion of the channel region by a firstoxide thickness; and at least one vertical control gate separated from asecond portion of the channel region by a second oxide thickness,wherein the at least one vertical control gate is parallel to andopposing the vertical floating gate; a number of address lines coupledto a control gate for the number of floating gate transistors and thevertical control gates for the logic cells; and a number of output linescoupled to a drain region for the number of floating gate transistorsand the logic cells, and wherein the number of output lines includes atleast one redundant row line.
 14. The decode circuit of claim 13,wherein the number of output lines coupled to a drain region for thenumber of floating gate transistors and the logic cells includes ap-channel metal oxide semiconductor (PMOS) load transistor coupledthereto.
 15. The decode circuit of claim 14, wherein the number ofoutput lines coupled to a drain region for the number of floating gatetransistors and the logic cells form an inverter in combination with thePMOS load transistor.
 16. The decode circuit of claim 15, wherein thenumber of programmable logic cells includes n-channel floating gatetransistors.
 17. The decode circuit of claim 13, wherein each verticalcontrol gate has a horizontal width of approximately 100 Angstroms (Å).18. The decode circuit of claim 13, wherein each vertical floating gateseparated from a first portion of the channel region includes a firstportion of the channel region which is adjacent to the source region,and wherein the each vertical control gate separated from a secondportion of the channel region includes a second portion of the channelregion which is adjacent to the drain region.
 19. The decode circuit ofclaim 13, wherein the each vertical control gate further includes ahorizontal member located above the vertical floating gate, wherein thevertical control gate and the horizontal member are separated from thevertical floating gate by an intergate dielectric.
 20. The decodecircuit of claim 13, wherein a capacitance between the vertical controlgate and the vertical floating gate is greater than a capacitancebetween the vertical floating gate and the channel region.
 21. Thedecode circuit of claim 13, wherein the number of floating gatetransistors include a number of floating gate transistors which areselectively coupled to the number of address lines.
 22. A memory addressdecoder, comprising: a number of thin oxide gate transistors having asource region, a drain region, and a channel therebetween; a number ofnon volatile memory cells, the non-volatile memory cells each,comprising: a horizontal substrate, wherein the substrate includes asource region, a drain region, and a channel region separating thesource and the drain region; a first vertical gate located above a firstportion of the channel region and separated from the channel region by afirst oxide thickness; a second vertical gate located above a secondportion of the channel region and separated from the channel region by asecond oxide thickness, and a third vertical gate located above a thirdportion of the channel region and separated from the channel region bythe second oxide thickness; a number of address lines coupled to thegates of the number of thin oxide gate transistors and at least one ofthe first, second, or third vertical gates in the non volatile memorycells; and a number of output lines coupled to the drain region of thenumber of thin oxide gate transistors and non volatile memory cells. 23.The memory address decoder of claim 22, wherein the memory addressdecoder further includes a number of p-channel metal oxide semiconductor(PMOS) transistors coupled to the number of output lines.
 24. The memoryaddress decoder of claim 22, wherein the second and the third verticalgates are on opposing sides of the first vertical gate.
 25. The memoryaddress decoder of claim 22, wherein the first vertical gate includes afloating gate and wherein the second and the third vertical gatesinclude control gates coupled to the number of address lines.
 26. Thememory address decoder of claim 22, wherein first vertical gate includesa control gate coupled to the number of address lines and wherein thesecond and the third vertical gates include floating gates.
 27. Thememory address decoder of claim 22, wherein each non-volatile memorycell further includes a horizontal gate member which couples the secondand the third vertical gates.
 28. A memory address decoder, comprising:a number of thin oxide gate transistors having a source region, a drainregion, and a channel therebetween; a number of non volatile memorycells, the non-volatile memory cells each, comprising: a horizontalsubstrate, wherein the substrate includes a source region, a drainregion, and a channel region separating the source and the drain region;a first vertical gate located above a first portion of the channelregion and separated from the channel region by a first oxide thickness;a second vertical gate located above a second portion of the channelregion and separated from the channel region by a second oxidethickness, and a third vertical gate located above a third portion ofthe channel region and separated from the channel region by the secondoxide thickness; a number of address lines coupled to the gates of thenumber of thin oxide gate transistors and at least one of the first,second, or third vertical gates in the non volatile memory cells; and anumber of output lines coupled to the drain region of the number of thinoxide gate transistors and non volatile memory cells, wherein theaddress lines and the output lines form an array.
 29. The memory addressdecoder of claim 28, wherein at least one of the non volatile memorycells is programmed with a charge on at least one of the first, second,or third vertical gate such that the non volatile memory cell iseffectively removed from the array.
 30. The memory address decoder ofclaim 28, wherein the memory address decoder is operatively coupled to acomputer system.
 31. The memory address decoder of claim 28, whereineach non volatile memory cell includes a flash memory cell.
 32. Thememory address decoder of claim 28, wherein each non volatile memorycell includes an electronically erasable and programmable read onlymemory (EEPROM) cell.
 33. An address decode circuit for a memory device,comprising: a number of thin oxide gate transistors having a sourceregion, a drain region, and a channel therebetween; a number of floatinggate driver transistors, each floating gate driver transistor,comprising: a horizontal substrate, wherein the substrate includes asource region, a drain region, and a channel region separating thesource and the drain region; a vertical floating gate located above afirst portion of the channel region adjacent to the source region andseparated from the channel region by a first oxide thickness; and avertical control gate located above a second portion of the channelregion adjacent to the drain region and separated from the channelregion by a second oxide thickness; a number of address lines coupled tothe gates of the number of thin oxide gate transistors and the verticalcontrol gates for the floating gate driver transistors; and a number ofoutput lines coupled to a drain region for the number of thin oxide gatetransistors and floating gate driver transistors; and wherein a greaterpercentage of a voltage applied to the vertical control gate appearsbetween the vertical floating gate and the channel than between thevertical control gate and the vertical floating gate.
 34. The addressdecode circuit of claim 33 wherein the address decode circuit includes aNOR address decoder.
 35. The address decode circuit of claim 33 whereinthe number of thin oxide gate transistors include a number of n-channelfloating gate transistors which are selectively coupled to the number ofaddress lines.
 36. The address decode circuit of claim 33 wherein theaddress decode circuit further includes a number of p-channel metaloxide semiconductor (PMOS) load transistors coupled to the number ofoutput lines.
 37. The address decode circuit of claim 33, wherein thenumber of output lines include at least one redundant row line.
 38. Theaddress decode circuit of claim 37 wherein the at least one redundantrow line is coupled to a CMOS inverter, and wherein the CMOS inverterincludes a PMOS load transistor and at least one of the floating gatedriver transistors having a vertical floating gate.
 39. The addressdecode circuit of claim 38, wherein a charge on the vertical floatinggate for the at least one floating gate driver transistor controls theoperation of the at least one redundant row line.
 40. The address decodecircuit of claim 33 wherein address decode circuit operates withoperating voltages on the vertical control gate of approximately 2Volts.
 41. The address decode circuit of claim 33, wherein the verticalfloating gates are programmable with a fixed charge using voltages ofless than 5.0 Volts.
 42. An electronic system, the electronic systemcomprising a memory address decoder array, comprising: a number of thinoxide gate transistors having a source region, a drain region, and achannel therebetween; a number of vertical floating gate transistorlogic cells, the logic cells comprising: a horizontal substrate, whereinthe substrate includes a source region, a drain region, and a channelregion separating the source and the drain region; a first vertical gateseparated from a first portion of the channel region by a first oxidethickness; and a second vertical gate separated from a second portion ofthe channel region by a second oxide thickness, wherein the secondvertical gate is opposing the first vertical gate; a number of addresslines coupled to the gates of the number of thin oxide gate transistorsand logic cells; and a number of output lines coupled to the drainregion of the number of thin oxide gate transistors and logic cells. 43.The electronic system of claim 42 wherein at least one of the logiccells is programmed with a fixed charge on the first vertical gate suchthat the logic cell is effectively removed from the array.
 44. Theelectronic system of claim 42, wherein at least one of the logic cellsis programmed with a fixed charge on the second vertical gate such thatthe logic cell is effectively removed from the array.
 45. The electronicsystem of claim 42 wherein at least one of the logic cells is programmedwith a minimal or no fixed charge on either the first vertical gate orthe second vertical gate such that the floating gate transistor iseffectively included in the array.
 46. The electronic system of claim42, wherein each logic cell includes an electronically alterable andprogrammable read only memory (EAPROM) cell.
 47. The electronic systemof claim 42 wherein the first vertical gate and the second vertical gatehave a horizontal width of approximately 100 nanometers (nm).
 48. Theelectronic system of claim 42, wherein the first oxide thickness isapproximately 60 Angstroms (Å), and wherein the second oxide thicknessis approximately 100 Angstroms (Å).
 49. The electronic system of claim42 wherein the first vertical gate separated from a first portion of thechannel region by a first oxide thickness includes a first portion ofthe channel region which is adjacent to the source region, and whereinthe second vertical gate separated from a second portion of the channelregion by a second oxide thickness includes a second portion of thechannel region which is adjacent to the drain region.
 50. The electronicsystem of claim 42, wherein the number of output lines include at leastone redundant row line.
 51. An electronic system, comprising: a memorydevice; a processor coupled to the memory; and wherein the memory deviceincludes a memory address decoder including: a number of thin oxide gatetransistors having a source region, a drain region, and a channeltherebetween; a number of non volatile memory cells, wherein each nonvolatile memory cell includes: a horizontal substrate, wherein thesubstrate includes a source region, a drain region, and a channel regionseparating the source and the drain region; a vertical floating gatelocated above a first portion of the channel region adjacent to thesource region and separated from the channel region by a first oxidethickness; and a vertical control gate located above a second portion ofthe channel region adjacent to the drain region and separated from thechannel region by a second oxide thickness a number of address linescoupled to the gates of the number of thin oxide gate transistors andnon volatile memory cells; and a number of output lines coupled to thedrain region of the number of thin oxide gate transistors and nonvolatile memory cells.
 52. The electronic system of claim 51 wherein thevertical floating gate and the vertical control gate include polysilicongates which are separated from one another by silicon dioxide (SiO₂).53. The electronic system of claim 51, wherein the vertical floatinggate and the vertical control gate each have a horizontal width ofapproximately 100 nanometers (nm).
 54. The electronic system of claim51, wherein the first oxide thickness is approximately 60 Angstroms (Å),and wherein the second oxide thickness is approximately 100 Angstroms(Å).
 55. The electronic system of claim 51, wherein a charge stored onthe vertical floating gate located above a first portion of the channelregion adjacent to the source region controls electrical conductionbetween the source regions and the drain regions in the horizontalsubstrate.
 56. The electronic system of claim 51, wherein the processoris coupled to the memory on a single die.
 57. The electronic system ofclaim 51, wherein the at least one redundant row line is coupled to aCMOS inverter, and wherein the CMOS inverter includes a PMOS loadtransistor and at least one of the non volatile memory cells.
 58. Theelectronic system of claim 51, wherein the number of output linesincludes at least one redundant row line, and wherein a charge on thevertical floating gate for at least one of the non volatile memory cellscontrols the operation of the at least one redundant row line.
 59. Amethod for forming a decode circuit, comprising: forming a number ofaddress lines; forming a number of output lines; forming a number logiccells having gates coupled to the address lines and drain regionscoupled to the output lines; and forming a number of non volatile memorycells at the intersections of the address lines and at least one outputline, wherein forming the number of non volatile memory cells includes:forming a source region, a drain region, and a channel regiontherebetween in a horizontal substrate; forming a first vertical gateseparated from a first portion of the channel region by a first oxidethickness; and forming a second vertical gate separated from a secondportion of the channel region by a second oxide thickness, whereinforming the second vertical gate forming the second vertical gateopposing the first vertical gate.
 60. The method of claim 59, whereinforming the decode circuit includes forming a NOR decode array.
 61. Themethod of claim 59, wherein forming each second vertical gate in the nonvolatile memory cells includes interconnecting the second vertical gatewith one of the address lines.
 62. The method of claim 59, whereinforming a second vertical gate separated from a second portion of thechannel region by a second oxide thickness includes forming the secondvertical gate above a second portion of the channel region adjacent tothe drain region.
 63. The method of claim 59, wherein forming each firstvertical gate includes forming a floating gate and forming the secondvertical gate includes forming a control gate.
 64. The method of claim59, wherein forming each first vertical gate includes forming a controlgate and forming the second vertical gate includes forming a floatinggate.
 65. The method of claim 59, wherein forming the first verticalgate separated from a first portion of the channel region by a firstoxide thickness includes a forming the first vertical gate above a firstportion of the channel region which is adjacent to the source region.66. The method of claim 59, wherein forming the first vertical gateincludes forming the first vertical gate such that a charge stored onthe first vertical gate controls conduction in the horizontal channelregion.
 67. A method for forming a memory address decoder, comprising:forming a number of thin oxide gate transistors having a source region,a drain region, and a channel therebetween; forming a number of nonvolatile memory cells, wherein forming the non-volatile memory cellsincludes: forming a source region, a drain region, and a channel regiontherebetween in a horizontal substrate; forming a first vertical gatelocated above a first portion of the channel region and separated fromthe channel region by a first oxide thickness; forming a second verticalgate located above a second portion of the channel region and separatedfrom the channel region by a second oxide thickness, and forming a thirdvertical gate located above a third portion of the channel region andseparated from the channel region by the second oxide thickness; forminga number of address lines coupled to the gates of the number of thinoxide gate transistors and non volatile memory cells; and forming anumber of output lines coupled to the drain region of the number of thinoxide gate transistors and non volatile memory cells.
 68. The method ofclaim 67, wherein forming the second and the third vertical gatesincludes forming the second and the third vertical gates on opposingsides of the first vertical gate.
 69. The method of claim 67, whereinthe forming the first vertical gate includes forming a floating gate andwherein forming the second and the third vertical gates includes formingcontrol gates.
 70. The method of claim 67, wherein forming the firstvertical gate includes forming a control gate and wherein forming thesecond and the third vertical gates includes forming floating gates. 71.The method of claim 67, wherein forming each non-volatile memory cellfurther includes forming a horizontal gate member which couples thesecond and the third vertical gates.
 72. The method of claim 67, whereinforming each non-volatile memory cell further includes forming eachnon-volatile memory cell such that a greater percentage of a voltageapplied to the second and the third vertical gates appears between thefirst vertical gate and the channel than between the first vertical gateand the second and the third vertical gates.
 73. The method of claim 67,wherein forming the first, second and the third vertical gates includesforming the first, second and the third vertical gates to each have ahorizontal width of approximately 100 nanometers (nm).
 74. The method ofclaim 67, wherein forming the first vertical gate separated from thechannel region by a first oxide thickness includes separating the firstvertical gate from the channel region by a first oxide thickness whichis approximately 60 Angstroms (Å) and wherein forming the second and thethird vertical gates separated from the channel region by a second oxidethickness includes separating the second vertical gate from the channelregion by a second oxide thickness which is approximately 100 Angstroms(Å).
 75. The method of claim 67, wherein forming the number of thinoxide gate transistors includes forming a number of floating gatetransistors which are selectively coupled to the number of addresslines.
 76. The method of claim 67, wherein forming the memory addressdecoder includes forming a number of CMOS inverters coupled to thenumber of output lines.
 77. The method of claim 67, wherein forming thenumber of output lines includes forming at least one redundant row line.78. The method of claim 77, wherein the method further includes couplingthe drain region for the number of non volatile memory cells to the atleast one redundant row line.
 79. A method for enabling error correctionin a decode circuit, having a number of non volatile vertical floatinggate transistors coupled to a redundant row line, comprising:selectively applying a first potential across a first thickness oxidebetween a vertical floating gate and a first portion of a horizontalsubstrate, the horizontal substrate including a source region and adrain region separated by a horizontal channel region, in order to addor remove a charge from the vertical floating gate; and enabling theredundant row line by applying a second potential to a vertical controlgate located above a second portion of the horizontal substrate, whereinthe vertical control gate is parallel to and opposing the verticalfloating gate.
 80. The method of claim 79, wherein selectively applyinga first potential across a first thickness oxide includes selectivelyapplying a first potential of less than 5 Volts.
 81. The method of claim79, wherein enabling the redundant row line by applying a secondpotential includes applying a second potential of approximately 2 Volts.82. The method of claim 79, wherein enabling the redundant row line byapplying a second potential to the vertical control gate includesenabling the redundant row when a minimal or no charge is present on thevertical floating gate.
 83. The method of claim 79, wherein selectivelyapplying a first potential across a first thickness oxide between avertical floating gate and a first portion of a horizontal substrate inorder to add or remove a charge from the vertical floating gate includescontrolling conduction in the horizontal channel.
 84. A method forenabling error correction in a decode circuit, having a number of nonvolatile vertical floating gate transistors coupled to a redundant rowline, comprising: selectively storing a limited charge on a verticalfloating gate above a horizontal channel region in the number of nonvolatile floating gate transistors, wherein selectively storing thelimited charge on the vertical floating gate controls addressing theredundant row line; and applying a potential to a vertical control gateopposing the vertical floating gate and above the horizontal channelusing a number of address lines.
 85. The method of claim 84, whereinapplying a potential to a vertical control gate opposing the verticalfloating gate includes applying a potential of approximately 2 Volts.86. The method of claim 84, wherein selectively storing a limited chargeon a vertical floating gate above a horizontal channel region in thenumber of non volatile floating gate transistors further includesprogramming the vertical floating by applying a potential of less than 5Volts to the vertical control gate.
 87. The method of claim 86, whereinapplying a potential of less than 5 Volts to the vertical control issuch that a greater percentage of the applied potential appears betweenthe vertical floating gate and the horizontal channel than between thevertical floating gate and the vertical control gate.
 88. The method ofclaim 84, wherein selectively storing a limited charge on a verticalfloating gate above a horizontal channel region includes selectivelystoring a limited charge on a vertical floating gate separated by afirst oxide thickness from the horizontal channel.
 89. The method ofclaim 88, wherein applying a potential to a vertical control gateopposing the vertical floating gate and above the horizontal channelincludes applying the potential to a vertical control gate separated bya second oxide thickness from the horizontal channel.
 90. The method ofclaim 89, wherein applying the potential to the vertical control gateseparated by the second oxide thickness includes applying the potentialto the vertical control gate separated by an oxide thickness which isgreater than the first oxide thickness.
 91. The method of claim 84,wherein the method further includes selectively removing a limitedcharge from a vertical floating gate above a horizontal channel regionin the number of non volatile floating gate transistors.
 92. The methodof claim 84, wherein selectively storing a limited charge on a verticalfloating gate above a horizontal channel region in the number of nonvolatile floating gate transistors includes disabling the non volatilefloating gate transistor in the decode circuit.